Many electronic systems have complex architectures that include many integrated circuits (IC's) that communicate with each other at increasingly higher data signal speeds. However, the higher speeds of data signals communicated between IC's may lead to signal degeneration in the form of pulse dispersion and inter-symbol interference (ISI) that may degrade the signal-to-noise ratio (SNR) of the data signals. One common way to compensate for such degeneration is to implement a decision feedback equalizer (DFE) circuit. However, conventionally configured DFE circuits may not operate at speeds fast enough for compensating for signal degeneration of high-speed data signals.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.